1. Technical Field
The present disclosure relates to a memory manager for managing a plurality of memories.
2. Discussion of the Related Art
Some memory system-on-chips (SoC) may integrate two or more main memory interfaces. For example, those interfaces may be DDR (double data rate) memory interfaces.
The architecture of an SoC memory subsystem is driven by bandwidth requirement considerations, availability of hardware and/or costs in terms of integrated circuit area. In some situations, the choice of memory system may be driven primarily by bandwidth considerations versus integrated circuit area costs.
Consider a scenario where DDR bandwidth consumption is considered to be about 4,500 Mb/s (megabytes per second). If a system-on-chip needs DDR controllers with a maximum DDR frequency of 1333 MHz, such a DDR may be able to deliver around 3200 MB/s. This is assuming, for example, a data efficiency of 60%. Accordingly, one DDR does not provide the requested bandwidth. As such, a two DDR based architecture can be used. Generally, systems with two DDR memory interfaces are known. However, such a system may have in some situations some disadvantages. Usually, a two DDR memory interface requires a manual buffer allocation. When the integrated circuit is programmed, the software designer is required to select in advance how the DDR memory is allocated This may result in a waste of DDR capacity or bandwidth. Further, this may complicate on-chip interconnect. Additionally, such an arrangement is not flexible if the integrated circuit has variable patterns of usage.